Digital Logic Semiconductor Families
By Stephen Bucaro
logic family refers to the way the semiconductors are designed to create gates.
The first highly popular logic family, available in 1964, was TTL (Transistor-Transistor Logic).
Because of the high power consumption of TTL, in 1968 CMOS (Complementary Metal Oxide
Semiconductor) logic was released. Technically you could consider relays and vacuum
tubes to logic families, but no-one considers them that.
TTL logic gates are made using bipolar junction transistors. Shown above is a simplified
implementation of a TTL NAND gate. If the both emitters of T1 are at logic 1, (+5V), there
will be very little potential difference between the base and emitter. If however, either
one of the inputs is taken to logic 0 (GND), the emitter that is at logic 0 will be at a
lower voltage than that supplied to the base by R1. This will make T1 conduct, causing it
to saturate and taking its collector to a low potential (less than 0.8V) and since this is
also connected to T2 base, T2 will turn off, making its collector voltage rise to near +Vcc
CMOS logic gates use N-channel and P-channel field effect transistors. Shown above is
a simplified implementation of a CMOS NAND gate. T1 and T2 are P channel MOSFETs and either
of them will be turned on when logic 0 is applied to its gate. T1 and T2 are connected in
parallel from Vcc to the output, so switching either of them on will result in a logic 1
at the output. T3 and T4 are N channel MOSFETs and either of them will be turned on when
a logic 1 to its gate. T3 and T4 are connected in series between the output and ground so
when both are switched on, a logic 0 will appear at the output. The ultimate logic level
at the output depends on the on or off state of the combination of all four transistors,
and that is controlled by the logic levels applied to the inputs A and B.
Because of high noise immunity and low power dissipation, CMOS transistors are preferred
in large scale integrated circuits. Because static electricity can easily destroy the
very thin insulating layer between the gate and the channel of the MOSFET transistor,
They require special handling and should always be stored in anti static packaging.