Round-Robin CPU Scheduling Algorithm
CPU Scheduling deals with the problem of deciding which of the processes in the ready queue is to be alocated the CPU. There are many different CPU scheduling algorithms. In this article we describe round-robin CPU scheduling. More ...
Intel's Core 2 Processors
Intel's Core 2 processors, released in July of 2006, are based on the Core microarchitecture, a dual core design using a 65nm manufacturing process to put 291 million transistors on a 143 square mm die. Each core has its own 64KB L1 cache. The two cores share an L2 cache that can be either 2MB or 4MB. More ...
Microcontroller Internal EEPROM (Electrically Erasable Programmable Read Only Memory) Memory
In some situations it is required that some program parameters such as configuration settings be keept after the system is powered off. This is made possible by including a EEPROM internally to the microcontroller. More ...
Fundamental Digital Logic Gates
All the advanced features of the most powerful computers, such as mulicore and parallel processing are done with digital logic. In this article I explain the fundamental concept of digital logic in simple and clear language so that anyone can understand it. More ...
Expanding the Resources of Microcontrollers
In some cases it is possible that the internal resources of a microcontroller are insufficient. The solution to these situations is to add external components by creating an expanded microcontroller structure. More ...
Digital Logic Transfer Characteristics
In the real world, gates don't transfer logic levels instantaneously. The time it takes for electrons and holes to move through the semiconductor material (called propagation delay) in CMOS are less than 100 ps (pico seconds), but there are other delays caused by resistance, capacitance, and inductance. More ...
Processor Interrupts
An interrupt is a signal to the processor indicating an event has occurred that needs immediate attention. When an interrupt occurs, the processors normal path of execution is interrupted in order to run a routine to service the interrupt requester. More ...
Intel's Sandy Bridge Micro-Architecture
"Sandy Bridge" is Intel's code name for a new cpu core microarchitecture. It introduces a few new or improved features. The memory controller, the PCI Express controller, and video circuitry are all located within the processor die and the new ring architecture uses a Last Level Cache between the CPU and graphics cores. More ...
Arduino Microcontroller Development Platform
The benefit of the open source Arduino Microcontroller Development Platform is that the software is free and the hardware is cheap. This makes it one of the cheapest platforms on which to develop prototypes. More ...
Operating System Memory Paging
Paging is a memory management scheme that permits a process's physical address space to be noncontiguous. More ...
Difference between Stack, Heap, and Queue
Stack, heap, and queue are ways that elements are stored in memory. Stack elements are added to the top of the stack, and removed from the top of the stack. The mnemonic LIFO is used to describe a stack (Last-In-First-Out). With a queue, the first one in is the first one out. The mnemonic FIFO is used to describe a queue. A heap is an area of memory where elements can be stored and removed in any order. More ...
Intel Celeron D Processor
The Celeron processor is a budget processor offering moderate performance at an affordable price. The Celeron processor is suitable for use in notebook and desktop computers running home-office applications and providing access to the Internet. More ...
