The Fetch, Decode, Execute Cycle
By Stephen Bucaro
The Fetch, Decode, Execute cycle is paramount to the functioning of a microprocessor. In this
article I'll describe the Fetch, Decode, Execute cycle simplified to its bare-bones in a highly
simplified fictitious microprocessor.
The Program Counter (PC) is a microprocessor register that simply counts. If the microprocessor
where executing a program that does nothing, the Program Counter would sequentially step
through memory addresses. However most programs don't sequentially step through memory
addresses, they loop and branch. Therefore the actual address of the location in memory
to be accessed is found in another register called the Memory Address Register (MAR). The
address in the MAR may come from the PC or from the Instruction Decoder (ID).
Lets design a very simple program to see how the Fetch, Decode, Execute cycle works.
1. ADD 5,6
2. STOR 3
The first thing the program does is fetch the instruction located at memory address 1.
To do this the MAR performs a memory read operation, causing the contents of memory
address 1 to be transferred over data bus to the ID.
The ID decodes the contents of memory address 1, determining that it is an ADD instruction,
and it's the type of ADD instruction that contains the values to be added in the second and
third parts of the instruction.
The ID, now knowing exactly what to do with the instruction it has received transfers the
values to be added to the input registers of the Arithmetic Logic Unit (ALU) and activates
control lines that cause the ALU to add the two values and place the results in its output
register. That instruction having been completed the PC increments to the next value and
places the value in the MAR.
This causes the instruction located at memory address 2 to be to be transferred over data
bus to the ID.