Welcome to Bucaro TecHelp!

Bucaro TecHelp
HTTPS Encryption not required because no account numbers or
personal information is ever requested or accepted by this site

About Bucaro TecHelp About BTH User Agreement User Agreement Privacy Policy Privacy Site Map Site Map Contact Bucaro TecHelp Contact RSS News Feeds News Feeds

Processor Interrupts

An interrupt is a signal to the processor indicating an event has occurred that needs immediate attention. When an interrupt occurs, the address in the processors program counter register (PC) and the content of the other processor registers are saved in a storage area called the stack. The processor then jumps to the address of the appropriate interrupt service routine (ISR) in the Interrupt Vector Table and begins executing the interrupt service routine, or interrupt handler.

After the interrupt service routine completes, the processor pulls the pre-interrupt program counter contents and other the processor registers contents off the stack, restores them to the proper registers, The processor then returns to executing the program that was running before the interrupt occurred.

Hardware Interrupt

A hardware interrupt is a signal sent from a hardware device to a connection called the interrupt request line. The signal alerts the processor that the device needs attention. For example, when a keyboard key is pressed it sends a hardware interrupt signal that causes the processor to perform the interrupt service as described above. The interrupt service routine for a keyboard key press would cause the processor to read the keys code and sent it to the application or operating system. Other hardware devices that use hardware interrupts are the mouse, a disk controller, communications port, or other external peripheral.

8259A Programmable Interrupt Controller (PIC)

8259A Programmable Interrupt Controller (PIC)

The 8259A Programmable Interrupt Controller (PIC) was designed to work with early Intel microprocessors. IR0-IR7 (Interrupt Request inputs): These are asynchronous interrupt request input pins. The chip can be programmed to accept level triggered or edge triggered interrupt requests, however, all interrupts must be triggered the same.

Nine 8259As can be cascaded in a master-slave configuration mode to handle 64 interrupt inputs. The CAS2-0 lines form a local 8259A bus to control multiple 8259As in master-slave configuration.

D7-D0 (Data Bus): Bidirectional data bus. Control, status and interrupt vector information is transferred via this data bus.

INT (Interrupt output): This pin goes high whenever a valid interrupt request is asserted. It is used to interrupt the CPU.

RSS Feed RSS Feed

Follow Stephen Bucaro Follow @Stephen Bucaro

Fire HD
[Site User Agreement] [Privacy Policy] [Site map] [Search This Site] [Contact Form]
Copyright©2001-2019 Bucaro TecHelp 13771 N Fountain Hills Blvd Suite 114-248 Fountain Hills, AZ 85268